1. Field of the Invention
The present invention relates to a sequence controller for controlling a sequence of operating states of a data processor and, more particularly, to a controller for designating a next operating state by a response signal to a current operating state.
2. Description of the Related Arts
Such a sequence controller may be employed in, for example, an instruction decoder unit of a microprocessor. More specifically, the microprocessor includes a bus control unit for controlling a bus coupled to a memory to write or read data into or from the memory, an instruction prefetch unit coupled to the bus control unit for prefetching instructions from the memory by use of the bus control unit, an effective address generator coupled to the bus control unit for supplying an effective address used for a memory access operation, an execution unit executing each instruction, and an instruction decoder unit coupled to the prefetch unit, the effective address generator and the execution unit. The decoder unit requests the prefetch unit to output the instruction therefrom. If the prefetch unit has the prefetched instruction, it returns a prefetch ready signal to the decoder unit and concurrently supplies the instruction to the decoder unit. The decoder unit responds to the prefetch ready signal and receives the instruction from the prefetch unit to decode it. In general, the instruction has an operation code field for designating an operation to be executed by the execution unit and at least one operand addressing field for designating the address of operand data to be processed. The decoded output of the operation code field is therefore supplied to the execution unit. On the other hand, in the case where the operand addressing field is decoded to designate a memory address, the decoder unit requests the effective address generator to calculate the effective address of the operand data. If the effective address generator is free, it returns an address calculation ready signal to the decoder unit and starts to calculate the effective address of the operand data. The calculated effective address is supplied to the bus control unit. In response to the address calculation ready signal, on the other hand, the decoder unit changes to an initial operating state to request the prefetch unit to output a next instruction.
Thus, the instruction decoder unit operates according to a predetermined state sequence. In order to control the operating sequence of the decoder unit, a sequence controller is provided, which includes a state designation circuit for designating the current operating state to be performed. It should be noted, however, that the current operating state has to be maintained until the response signal to the current operating state, i.e. the prefetch ready signal or the address calculation ready signal, is returned to the sequence controller. For this purpose, according to the above prototype sequence controller, the output of the state designation circuit is latched by a latch circuit in synchronism with a first clock signal, the output of the latch circuit being used for designating the current operating state, and the response signal to the current operating state is sampled in synchronism with a second clock signal having a phase opposite to that of the first clock signal. The sampled result is supplied to the state designation circuit together with the output of the latch circuit. When the response signal is not returned, the state designation circuit designates the same operating state, so that the output of the latch circuit is not changed.
However, the sampling of the response signal is carried out in synchronism with the second clock signal, i.e., in synchronism with the end of a half clock of the first clock signal. It is very difficult to synchronize the operations of the prefetch unit and the effective address unit, because they operate at a very high speed to return the ready signal to the decoder unit within the period corresponding to the half clock of the first clock signal. In fact, they return the ready signal to the decoder unit after the half clock of the first clock signal. For this reason, the same operating state is designated during at least two clock periods of the first clock signal even when the prefetch unit and the effective address generator return the ready signal to the decoder unit immediately in response to the request from the decoder unit. As a result, the data processing speed of the microprocessor cannot be made faster.